1. Field of the Invention
The present invention relates to data processor storage systems and more particularly to dynamic storage systems for multiprocessor systems.
2. Description of the Prior Art
The following are systems representative of the prior art.
U.S. Pat. No. 4,365,295 shows a multiprocessor system including a memory system in which the memory of each processor module is divided into four logical address areas. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system.
This patent which describes a conventional memory mapping system, does not address the efficient access of memory by single or multiple processors including interleaving storage references by a processor and dynamically directing storage references to global or local portions of each storage module.
U.S. Pat. No. 4,228,496 shows a multiprocessor system including a memory system as above to implement a virtual memory system.
However, this patent which describes a conventional memory mapping system, does not address the efficient access of memory by single or multiple processors including interleaving storage references by a processor and dynamically directing storage references to global or local portions of each storage module.
U.S. Pat. No 4,174,514 shows apparatus for performing neighborhood transformations on data matrices for image processing and the like achieving processing speeds greater than serial processors within a economy of memory through use of a plurality of serial neighborhood processors that simultaneously operate upon adjoining partitioned segments of a single data matrix.
This patent shows a multiprocessor system without any provision for access by all processors to a common global storage.
U.S. Pat. No. 4,121,286 shows apparatus for allocating and deallocating memory space in a multiprocessor environment.
This patent which describes a conventional memory mapping system, does not address the efficient access of memory by single or multiple processors including interleaving storage references by a processor and dynamically directing storage references to global or local portions of each storage module.
U.S. Pat. No. 3,916,383 shows a resource allocation circuit selectively activating individual processors by time slice basis where a time slice has approximately the same time duration as the system storage time. The resource allocation circuit includes a priorty network which receives real time common resource utilization requests from the processors according to the individual processor needs, assigns a priorty rating to the received request and alters in response thereto the otherwise sequential activation of the processors. The patent shows a system with several independent data processors within a single central processor which is not a true multiprocessor system in the usual sense.
The present invention relates to a system having one or more independent processors forming a multi
processor in which a storage system is dynamically partitioned into global storage and local storage.
U.S. Pat. No. 3,820,079 shows a multiprocessing computer structured in modular form around a common control and data bus. Control functions for the various modules are distributed among the modules to facilitate system flexibility. The patent shows a system including conventional memory mapping and interleaving.
Unlike the present invention, the memory mapping does not control the interleaving and the interleaving is the same over all modules for all data.
U.S. Pat. No. 3,641,505 shows a multiprocessor computing system in which a number of processing units, program storage units, variable storage units and input/output units may be selectively combined to form one or more independent data processing systems. System partitioning into more than one independent system is controlled alternatively by manual switching or program directed partitioning signals.
This patent which describes a conventional memory mapping system, does not address the efficient access of memory by single or multiple processors including interleaving storage references by a processor and dynamically directing storage references to global or local portions of each storage module.
U.S. Pat. No. 3,601,812 shows a memory system for buffering several computers to a central storage unit or a computer to several small memory units and a partitioned address scheme for the efficient use thereof. The digits of the address are decomposed into two disjoint subsets one of which is used as a buffer memory address and the other of which is stored with data word to effect identification thereof.
The patent deals with buffering memory data in a multiprocessor and does not show a dynamically partitioned storage system including interleavings storage references by a processor and directing dynamically storage references to global or local portions of storage.
The prior art discussed above does not teach nor suggest the present invention as disclosed and claimed herein.